SPLASH 2025
Sun 12 - Sat 18 October 2025 Singapore
co-located with ICFP/SPLASH 2025
Sat 18 Oct 2025 15:00 - 15:15 at Orchid West - Verification 3 Chair(s): KC Sivaramakrishnan

This paper concerns the problem of checking if two shallow (i.e., constant-depth) quantum circuits perform equivalent computations. Equivalence checking is a fundamental correctness question—needed, e.g., for ensuring that transformations applied to a quantum circuit do not alter its behavior. For quantum circuits, the problem is challenging because a straightforward representation on a classical computer of each circuit’s quantum state can require time and space that are exponential in the number of qubits $n$.

The paper presents \emph{Projection-Based Equivalence Checking} (PBEC), which provides decision procedures for two variants of the equivalence-checking problem. Both can be carried out on a classical computer in time and space that, for any fixed depth, is linear in $n$. Our key insight is that local projections can serve as constraints that fully characterize the output state of a shallow quantum circuit. The output state is the unique quantum state that satisfies all the constraints. Beyond equivalence checking, we show how to use the constraint representation to check a class of assertions, both statically and at run time. Our assertion-checking methods are sound and complete for assertions expressed as conjunctions of local projections.

Our experiments showed that computing the constraint representation of a random 100-qubit 1D circuit of depth 6 takes 129.64 seconds. Equivalence checking between two random 100-qubit 1D circuits of depth 3 requires 4.46 seconds for fixed input $\ket{0}^{\otimes 100}$, and no more than 31.96 seconds for arbitrary inputs. Computing the constraint description for a random 100-qubit circuit of depth 3 takes 6.99 seconds for a 2D structure, compared to 10.67 seconds for a circuit with arbitrary connectivity. At depth 2, equivalence checking takes 0.20 seconds for fixed input and 0.44 seconds for arbitrary input, with similar performance for both 2D and arbitrary-connectivity circuits.

Sat 18 Oct

Displayed time zone: Perth change

13:45 - 15:30
Verification 3OOPSLA at Orchid West
Chair(s): KC Sivaramakrishnan IIT Madras and Tarides
13:45
15m
Talk
Automated Verification of Soundness of DNN Certifiers
OOPSLA
Avaljot Singh UIUC, Yasmin Chandini Sarita UIUC, Charith Mendis University of Illinois at Urbana-Champaign, Gagandeep Singh University of Illinois at Urbana-Champaign; VMware Research
14:00
15m
Talk
Bolt-On Strong Consistency: Specification, Implementation, and Verification
OOPSLA
Nicholas V. Lewchenko University of Colorado Boulder, Gowtham Kaki University of Colorado at Boulder, Bor-Yuh Evan Chang University of Colorado Boulder & Amazon
14:15
15m
Talk
Memory-Safety Verification of Open Programs With Angelic Assumptions
OOPSLA
Gourav Takhar Indian Institute of Technology - Kanpur, Baldip Bijlani Indian Institute of Technology Kanpur, Prantik Chatterjee MathWorks, Akash Lal Microsoft Research, Subhajit Roy IIT Kanpur
14:30
15m
Talk
Mini-Batch Robustness Verification of Deep Neural Networks
OOPSLA
Saar Tzour-Shaday Technion – Israel Institute of Technology, Dana Drachsler Cohen Technion
14:45
15m
Talk
Revamping Verilog Semantics for Foundational VerificationDistinguished Paper
OOPSLA
Joonwon Choi Amazon Web Services, Jaewoo Kim KAIST, Jeehoon Kang FuriosaAI
15:00
15m
Talk
Scalable Equivalence Checking and Verification of Shallow Quantum Circuits
OOPSLA
Nengkun Yu Stony Brook University, USA, Xuan Du Trinh Stony Brook University, Thomas Reps University of Wisconsin-Madison
15:15
15m
Talk
Structural temporal logic for mechanized program verification
OOPSLA
Lef Ioannidis University of Pennsylvania, Yannick Zakowski Inria, Steve Zdancewic University of Pennsylvania, Sebastian Angel University of Pennsylvania
Hide past events